Techniques to form more highly integrated circuits frequently utilize photolithographically-defined patterning steps to define circuit features having reduced lateral dimensions. However, because the tolerances associated with photolithographic alignment steps do not necessarily scale downward with the continued reductions in lateral dimensions of current state-of-the-art integrated circuit devices, the formation of contact holes during back-end processing steps may cause unacceptably high rates of failure and unacceptably low yields when chips embodying the integrated circuit devices are tested. This is particularly true in fabrication techniques requiring the formation of relatively high aspect ratio contact holes, which are to be filled with electrical interconnects. As will be understood by those skilled in the art, even slight deviations in photolithographic alignment may cause formation of electrical shorts between electrical interconnects in relatively deep contact holes and surrounding active and passive device structures, including multi-level wiring.
One example of a contact formation technique having self-aligned characteristics is disclosed in U.S. Pat. No. 7,875,551 to Lee et al., entitled “Methods of Forming Integrated Circuit Devices Using Contact Hole Spacers to Improve Contact Isolation,” the disclosure of which is hereby incorporated herein by reference. Another example of a contact formation technique having self-aligned characteristics is disclosed in U.S. Pat. No. 6,881,659 to Park et al., entitled “Methods of Forming Self-Aligned Contact Structures in Semiconductor Integrated Circuit Devices,” the disclosure of which is hereby incorporated herein by reference.